1. Field of the Invention
The present invention relates to the field of computer systems, in particular, uniprocessor computer systems having cache memory and allowing direct memory accesses by input/output devices. More specifically, the present invention relates to methods and apparatus employed by these systems to maintain cache coherency.
2. Background
Cache memory is well known in the art. Historically, the early caches were introduced at a time when memory was accessed exclusively by the (central processing unit (CPU). For obvious performance reasons, these early caches tended to be write back caches. With the advent of direct memory access by the input/output devices, many of the caches employed were switched to write through caches. A write through cache was and still is a simple way to side step the issue of maintaining cache coherency between the cache and main memory. The obvious drawback is that the performance advantage of write back cache from making fewer memory accesses is sacrificed.
It would, of course, be preferable to implement a write back cache so the above mentioned sacrifice could be avoided, particularly on multiprocessor systems. As a result, various cache coherency protocols were developed in the industry. Among them is the four state (modify, exclusive, shared, and invalid) MESI protocol (see FIG. 1). Under the MESI protocol, the cache memory is actually a hybrid write back/write through cache with the write back characteristic determined on a line by line basis. In recent years, the MESI protocol has actually emerged as one of more widely accepted industry standards, particularly for microprocessor based multiprocessor systems.
As technology continues to drive down the cost of microprocessor based computer systems allowing more functions to be provided, it is not uncommon to find these days that even the low end microprocessor based uniprocessor systems are provided with cache memory. For many of these uniprocessor systems, in order to exploit the performance advantage of write back cache, the same MESI protocol is employed to maintain cache coherency. Since the MESI protocol was originally designed for multiprocessor systems, it contains functions that are unnecessary for uniprocessor systems. In other words, the MESI protocol is more complicated and more costly than necessary for the uniprocessor environment. Therefore, for other uniprocessor systems, attempts have been made to develop and employ simpler and lesser cost cache coherency protocols. A particular example is the three state (modified, valid, and invalid) MVI protocol (see FIG. 1b). However, protocols such as the three state MVI protocol have the disadvantage of requiring additional auxiliary configuration registers to be employed if the function of determining write characteristic on a line by line basis is provided. The additional auxiliary configuration registers are undesirable in a number of ways. First of all, they require additional look ups to determine whether write backs to memory should be performed immediately or they can be deferred. The additional look ups impact performance. Secondly, they require real estate. The real estate requirement is particularly undesirable if the cache memory is to be integrated as part of the microprocessor chip, commonly known as on-chip cache.
Thus, it is desirable to provide a cache coherency protocol for a uniprocessor system that is less complicated and less costly than the four state MESI protocol, however, without the disadvantages of the three state MVI protocol. As will be disclosed, the streamlined four state hybrid write back/write through cache of the present invention advantageously achieves the above described desired results.